General Chair

Matthew Guthaus, UC Santa Cruz, USA

Program Chair

Ayse Coskun, Boston Univ., USA

Andreas Burg, EPFL, Switzerland

Special Sessions Chairs

Jose Renau, UC Santa Cruz, USA

Sung-Mo (Steve) Kang, UC Santa Cruz, USA

Publication Chair

Srinivas Katkoori, Univ of South Florida, USA

Ricardo Reis, UFRGS, Brazil

Publicity Chair Ricardo Reis, UFRGS, Brazil
Registration Chair

Rajsaktish Sankaranarayanan, UC Santa Cruz, USA

Finance Chair Baris Taskin, Drexel, USA
PhD Forum Chair Ken Pedrotti, UC Santa Cruz, USA
Steering Committee

Manfred Glesner — TU Darmstadt, Germany
Salvador Mir — TIMA, France

Ricardo Reis — UFRGS, Brazil

Michel Robert — U. Montpellier, France

Luis Miguel Silveira — INESC ID, Portugal

Chi-Ying Tsui — HKUST, Hong-Kong

Technical Program Committee

T1 Analog and mixed-signal IC design

Jerzy Dabrowski, Linköping University, Sweden
Jose M. de la Rosa, University of Seville, Spain
Pawel Grybos, University of Science and Technology, Poland
Rashad Ramzan, FAST National University of Computer and Emerging Sciences, Pakistan
Ryszard Wojtyna, University of Technology and Agriculture, Bydgoszcz, PL
S. Pavan, Indian Institute of Technology, India
Piero Malcovati, University of Pavia, Italy
Pui-In Mak, University of Macau, Macau

T2 Microsystems and integrated MEMS for bio-electronics and bio-sensing

Mohamad Sawan, École Polytechnique de Montréal, Canada
Urs Frey, RIKEN QBiC, Japan
George-Jie Yuan, Hong Kong Univ. of Science and Tech., Hong Kong
Libor Rufer, TIMA Laboratory, France
Fan-Gang Tseng, National Tsing-Hua University, Taiwan ROC
Jun Ohta, Nara Institute of Science and Technology, Japan
Andreas Demosthenous, University College London, UK
Andrew Mason, Michigan State University, USA
Dongsheng Ma, The University of Texas at Dallas, USA

T3 Design for variability, reliability, fault tolerance, and test

Matteo Sonza Reorda, Politecnico di Torino, Italy
Ozgur Sinanoglu, NYU Abu Dhabi, UAE
Xiaoqing Wen, Kyushu Institute of Technology, Japan
Haralampos Stratigopoulos, Laboratoire TIMA, France
Fernanda Kastensmidt, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil
Mohammad Tehranipoor, University of Connecticut, USA
Seiji Kajihara, Kyushu Institute of Technology, Japan
Georgios Karakonstantis, EPFL, Switzerland

T4 Circuits and systems for DSP, image processing, and communications

Luc Claesen, Univ. Hasselt, Belgium
Mario Vigliar, DPControl
Danilo Pau, STMicroelectronics
Peng Liu, Zhejiang University, China
Chun-Jen Tsai, NCTU, Taiwan
Marilyn Wolf, Geogia Tech., USA
Christos Bouganis, Imperial College, UK
Leandro Soares Indrusiak, Univ. of York, UK
Nam Pham Ngoc, Hanoi University of Science and Technology, Vietnam

T5 Emerging technologies and new devices for large-scale integration

Paul Franzon, North Carolina State Univ., USA
Kaushik Roy, Purdue University, USA
Prof. Saibal Mukhopadhyay, Georgia Tech, USA
Dr. Swaroop Ghosh, Intel Corp, USA.
Jeff Wang, Johns Hopkins Univ., USA
Neil DiSpigna, North Carolina State Univ., USA
Dimitri Strukov, University of California Santa Barbara, USA
Quing-An Huang, SEU, China

T6 Prototyping, verification, and silicon debug for VLSI-SoCs

Franco Fummi, University of Verona, Italy
Masahiro Fujita, University of Tokyo, Japan
Virendra Singh, Indian Institute of Technology, India
Graziano Pravadelli, UNIVR, Italy
Laurence Pierre, IMAG, France
Sean Safarpour, Vennsa

T7 2D- and 3D-interconnect architectures and topologies including NoCs

Ian O'Connor, Ecole Centrale de Lyon, France
David Atienza, EPFL, Switzerland
Fabien Clermidy, CEA-LETI, France
Eby Friedman, Univ. of Rochester, USA
Sung Kyu Lim, Georgia Tech., USA
Terrence Mak, Newcastle University, UK
Sri Parameswaran, Univ. of New South Wales, Australia
Xiaoxia Sherry Wu, Qualcomm, USA

T8 System-on-chip design, embedded VLSI systems, and multi-core systems

Sergio Bampi, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil
Gabriela Nicolescu, Polytechnique Montreal, Canada
Michael Huebner, Karlsruhe Inst of Technology, Germany
Radu Marculescu, CMU
Frederic Rousseau, TIMA Laboratory, France
Soontae Kim, KAIST, Korea
Eugenio Villar, University of Cantabria, Spain
Flavio Wagner, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil

T9 Reconfigurable systems, application specific processors, FPGAs (Architectures and Tools)

Luigi Carro, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil
Juergen Becker, Karlsruhe Institute of Technology, Germany
Pascal Benoit, LIRMM, France
Koen Bertels, TU Delft, Netherlands
Reiner Hartenstein, TU Kaiserslautern, Germany
Patrick Lysaght, Xilinx, USA

T10 Transistor-level digital VLSI circuits and memories

Lionel Torres, University Montpellier 2, France
Massimo Alioto, University of Siena, Italy
Marc Belleville, CEA-LETI, France
Shoushun Chen, Nanyang Technological University, Singapore
Alexander Fish, University of the Negev, Israel
Joachim Rodrigues, Lund University, Sweden
Armin Tajalli, EM Microelectronics, Switzerland
Yajun Ha, National University of Singapore, Singapore
Koushik Maharatna, University of Southampton, UK
Mohammad Baker, Khalifa University, UAE

T11 Logic and high-level synthesis, SW synthesis, HW-SW co-design

Philip Brisk, University of California Riverside, USA
Andreas Gerstlauer, University of Texas Austin, USA
Philippe Coussy, Universite de Bretagne Sud, France
Elena Dubrova, Royal Institute of Technology, Sweden
Tulika Mitra, National University of Singapore, Singapore
Jason Anderson, University of Toronto, Canada
Gunar Schirner, Northeastern University, USA
Brett Meyer, McGill University, Canada
Taemin Kim, Intel Labs, USA

T12 Low-Power and Temperature-Aware Design

José Ayala, Complutense University of Madrid, Spain
Sherief Reda, Brown University, USA
Jose M. Moya, Technical University of Madrid, Spain
Joaquin Recas, Complutense University of Madrid, Spain
Lin Xie, Cadence, USA
Christian Piguet, CSEM, Switzerland
Mirko Loghi, University of Udine, Italy
Gang Qu, University of Maryland, USA
Lin Yuan, Synopsys, USA