Program Schedule
- Sunday, October 7, 2012
- 3pm-5pm, WG 10.5 Member Meeting (Beach View room)
- 5pm-7pm, VLSI-SOC 2012 TPC Meeting (Beach View room)
- 7pm-9:30pm, Welcome Reception
- Monday-Wednesday
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Yusuf Leblebici, EPFL, Director of Microelectronic Systems Laboratory |
Design and Testing Strategies for Modular 3D-Multiprocessor Systems Using Die-level TSV Technology This talk offers a broad overview on 3D integration technologies, and also provides some outline / insight concerning architectural design implications. An innovative modular 3D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by Through-Silicon-Vias (TSVs). Each die features four 32-bit embedded processors and associated memory modules, interconnected by a 3D Network-on-Chip (NoC), which can route packets in the vertical direction. To demonstrate the feasibility of this architecture, fully functional samples have been fabricated using a conventional UMC 90nm CMOS process and stacked using an in-house, Via-Last Cu-TSV process. Initial results show that the proposed 3D-CMP is capable of operating at a target frequency of 400 MHz, supporting a vertical data bandwidth of 3.2 Gbps. |
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Luigi Capodieci, GLOBALFOUNDRIES, Director of DFM/CAD |
A roadmap for DFM and Physical Design at the limits of IC scaling
While performance scaling for integrated circuits, as predicted, or rather "prescribed" by Moore's Law, continues all the way down to 28 and 20nm technology nodes (and possibly beyond), the geometric scaling of the actual circuit features (Critical Dimensions) is facing its ultimate physical limits with respect to manufacturability and yield. The unsung hero of this arduous challenge to keep IC performance on-track has been and continues to be a heterogeneous set of computationally intensive CAD methodologies collectively known as Design-Technology-Co-Optimization or Design-For-Manufacturing (DFM). The abstraction layer of the Design-Rule-Manual, and its Process Design Kit (PDK) collaterals, has evolved from a brick-wall separating IC Design and IC Manufacturing communities, into a two-way collaboration tool, where successful leading-edge designs require (and benefit from) in-depth knowledge of manufacturing processes, and conversely, high yielding process technologies are "design-aware" i.e. adapt to specific design styles and requirements. This presentation will illustrate the core set of methodological innovations in Design Enablement flows which are being introduced at 28 and 20nm, particularly advanced DFM physical verification and DFM-aware router implementations. Prominent examples are Manufacturability Scoring, model-based process verification and the industry first pattern-matching based hybrid verification (DRC+). In spite of the successful deployment of these DFM techniques, extreme low-k1 patterning and next generation (or non-traditional) lithographies will introduce a "variability challenge" for nodes at or below 14nm. This variability, intrinsically due to the interaction of physical design features and process characteristics requires a re-thinking of both IC physical design structure and organization, extending into architectural and system design. A physical design roadmap will be proposed to guide further evolution from the time-consuming and extremely expensive manufacturing verification of today into a "manufacturable-by-construction" flow of tomorrow. |
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Erik Brunvand, University of Utah, Associate Professor |
High Performance Ray Tracing: Implications for System Architectures The desire for ever more complex and realistic graphics drives the computer graphics hardware industry. This interest in high-quality rendering spans the range of computer hardware from high-end gaming machines and scientific workstations to small embedded platforms such as tablets and phones. While traditional graphics rendering using a Z-buffer rasterization algorithm is well supported with commercial graphics processing units (GPUs), the desire to improve image quality encourages a new look at an alternative rendering algorithm: ray tracing. Ray tracing more naturally handles a variety of optical effects that increase apparent realism in generated images, but has very different computational, I/O, memory, and power profiles than Z-buffer rasterization. As an example, traditional GPUs typically use wide Single Instruction Multiple Data (SIMD) processing to exploit the parallel behavior of Z-buffer rasterization. Ray tracing has a fundamentally different parallel character, and does not naturally map to a SIMD approach. System architectures that allow more flexibility in thread parallelism can perform much better for this type of application. In this talk I will describe and compare the two algorithms and discuss the impact of using ray tracing on the design of application specific processors. |
Special Session: Memristive Computing
Memristors and memristive devices have been recently realized in nanoscale. Several recent implementations have brought forth the potential for revolutions in non-volatile storage and reconfigurable computing. This special session is specifically focused at using memristive devices for computing in programmable systems such as FPGAs.
Special Session: Open Source Tools and Methodologies for Research
Open source tools enable both academia and industry to research, develop, and share common platforms in complex research tasks. However, most often these open source tools and methodologies are unsung and, in fact, difficult to publish. This special session is specifically focused at recognizing the most important and useful open source tools and methodologies that aid research.
Embedded Tutorial: Silicon Photonics Circuits and Architectures for Many-Core Systems
Organizer: Ajay Joshi, Boston University, USA
Speakers:
Ajay Joshi, Boston University, USA
Ron Ho, Oracle, USA
Matthew Farrens, UC Davis, USA
Silicon Photonics Circuits and Architectures for ManyCore Systems
Links based on silicon-photonic technology have been proposed as a potential replacement for electrical links in the on-chip and off-chip communication networks of manycore systems. In this three-part tutorial, we will discuss the various limits, opportunities and challenges associated with designing silicon-photonic networks for manycore systems. In the first part, we will discuss the challenges associated with designing transceiver circuit of a silicon-photonic link. In particular, we will present digitally-assisted analog techniques to reduce total power of optical receivers, discuss the SNR vs BER vs power tradeoff that can be exploited during receiver design, and present the circuit-level thermal tuning challenges associated with external- and self-heating of photonic devices. In the second part of the tutorial we will present an integrated approach to designing silicon photonic networks. We will emphasize the need for an iterative design process, where we move between different levels (physical level, micro-architecture level and architecture level) of design hierarchy to meet the power-performance specifications under the silicon-photonic technology constraints. This will be followed by a discussion of run-time techniques for management of laser power. The last part of the tutorial will involve the discussion of designing resilient silicon-photonic networks under thermal and process variations. This will be followed by a discussion of the impact of the mismatch between scaling of electronic devices and photonic devices, on the silicon-photonic network architecture.
Panel Session: Analog VLSI Design at the End of CMOS Scaling: What is ahead?
Organizer: Sergio Bampi, UFRGS, Brazil
Speakers: TBD
As the end of CMOS two-dimensional scaling nears, analog designers in the ultra-large scaled systems are facing new design challenges. Diminishing returns from voltage and transistor 2D scaling settled in at much earlier CMOS generations, at least for the analog VLSI. Large device variability and diminishing supply voltages make scaling not only challenging but not profitable for analog, in terms of area and final yield. Performance of mixed-signal circuits can in turn benefit in very different ways from alternative technology paths for SoC integration. These alternatives come from system-in-package (SIP), 3D integration of diverse substrates, and opto/sensor heterogeneous integration to analog CMOS. Panelists will address at least one of the following issues:
- Since ultra-large-Digital/small-Analog SoCs are in high demand at decananometer SoCs, what is ahead for the analog CMOS VLSI designers?
- What are the key innovations on analog design required to support the voltage and dimensional scaling of latest-node processors and memories?
- Will variability at 22nm and below require "no-scaling" rules for the analog blocks?
- Analog supplies stop at 1V for RF CMOS?
- What are the impacts of choosing the alternative integration paths listed above for the integration of analog CMOS into heterogeneous SIPs?
Best Paper Award
The best paper award was given to:
Neil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra and Paul Franzon. A Novel Double Floating-Gate Unified Memory Device
Other best paper nominees included:
- Davide Sabena, Matteo Sonza Reorda and Luca Sterpone. A new method for the automatic generation of optimized Software-Based Self-Test programs for VLIW processors
- Jeremy Constantin, Ahmed Dogan, Oskar Andersson, Pascal Meinerzhagen, Joachim Neves Rodrigues, David Atienza and Andreas Burg. An Ultra-Low-Power Application-Specific Processor for Compressed Sensing
- Seokjoong Kim and Matthew Guthaus. Dynamic Voltage Scaling for SEU-Tolerance in LowPower Memories